Introduction
Non-volatile memory — memory that retains data without power — is one of the most critical components in embedded systems, from industrial PLCs and MCUs to IoT sensors and edge AI processors. Today, Flash memory (NAND and NOR) dominates the embedded non-volatile memory market. But Flash has fundamental physical and performance limitations that are becoming increasingly problematic as embedded systems become more demanding.
Resistive RAM (ReRAM) — also known as RRAM or memristive memory — is one of the more promising next-generation non-volatile memory technologies, and it is moving from academic research toward commercial deployment in 2025–2026. Weebit Nano, one of the leading ReRAM IP companies, presented at Embedded World 2026 making the case for replacing Flash in embedded applications.
I should say where I am standing. I build robotics, UAV and industrial-automation systems and the software around them; I am not a memory designer, and this is analysis of published material rather than a first-hand account of qualifying ReRAM in a product.
But this is the topic in this series where the downstream view is genuinely the more useful one, because memory endurance is not really a specification — it is a failure mode with a countdown attached, and failure modes are the part of a system I do think about directly. An industrial device that logs continuously is spending its write budget from the moment it is commissioned, and the interesting question is what happens at the end of that budget, and what happens if power is lost halfway through a write.
The Fundamental Limitations of Flash Memory in Embedded Applications
Flash memory operates by storing charge in a floating gate or charge trap layer to represent a binary data state. Reading data requires sensing the stored charge. Writing data requires programming (adding charge) or erasing (removing charge) using relatively high voltages that differ from the chip's standard operating voltage.
This physics imposes several limitations that are increasingly relevant for modern embedded applications:
Write Endurance: Every write/erase cycle slightly degrades the gate oxide that retains the stored charge. NAND Flash typically supports 3,000–10,000 program/erase cycles before the bit error rate becomes unacceptable. NOR Flash supports 100,000 cycles for most devices. For data that changes frequently — sensor logs, AI model weights being updated, runtime configuration data — Flash endurance can be a real design constraint requiring wear-leveling algorithms, spare block management, and careful write minimization.
Write Speed: Flash memory writes are slow. NOR Flash page program times are typically 50–200 microseconds per page. NAND Flash is faster in burst mode but requires complex block management with erase-before-write operations. For applications requiring frequent writes at high speed — data logging at high sample rates, frequent firmware updates, rapid AI model switching — Flash write latency is a bottleneck.
Byte Addressability: NAND Flash is not byte-addressable — it must be written and erased in blocks. This requires a file system layer (FAT, LittleFS, SPIFFS) between the application and the physical memory, adding software complexity, RAM overhead, and latency. NOR Flash is byte-programmable but still requires block erase operations, limiting flexibility.
Operating Temperature: Standard Flash memory is rated to -40°C to +85°C. Industrial Flash extends to -40°C to +105°C for some devices. But at the extreme temperatures of certain industrial environments — engine bay controllers, downhole sensors, aerospace systems — even industrial Flash reliability degrades unacceptably. Data retention (the ability to hold charge without power) also degrades at elevated temperature.
How ReRAM Works — The Physics of Resistive Switching
ReRAM stores information as the resistance state of a thin film of material placed between two electrodes. The material — typically a metal oxide such as hafnium oxide (HfOx), tantalum oxide (TaOx), or titanium oxide (TiOx) — can be switched between a high-resistance state (representing binary 1) and a low-resistance state (representing binary 0) by applying appropriate voltage pulses.
The physical mechanism involves the formation and dissolution of conductive filaments — paths of oxygen vacancies or metallic ions — through the oxide layer. A "set" operation forms the filament (switching to low resistance). A "reset" operation dissolves the filament (switching to high resistance). The energy required for filament formation and dissolution is extremely small compared to the charge injection/removal in Flash, which has direct implications for programming voltage, write speed, and endurance.
Because ReRAM switching is a purely resistive phenomenon (no floating gate, no charge storage), it does not suffer from the same gate oxide degradation that limits Flash endurance. Endurance values of 10^9 to 10^12 cycles have been demonstrated in research settings — orders of magnitude better than Flash. Commercial ReRAM products target 10^6 to 10^8 cycle endurance, already 100x–10,000x better than NOR Flash.
ReRAM vs Flash — A Direct Performance Comparison
The performance advantages of ReRAM over Flash are significant for specific embedded use cases:
Write Speed: ReRAM write operations complete in nanoseconds to microseconds — 100x to 1000x faster than NOR Flash page program. For applications that write frequently or require low-latency data commitment, this is a transformative improvement.
Endurance: Commercial ReRAM targets 10^6 to 10^8 write cycles versus 100,000 cycles for NOR Flash. This eliminates wear-leveling requirements for most applications and dramatically simplifies firmware design.
Operating Voltage: ReRAM operates at standard CMOS supply voltages (1.2V–1.8V) for read operations, with programming voltages in the 1.5V–3V range — compatible with advanced logic process nodes and much lower than Flash programming voltages (12V+). This enables tight integration with logic circuits on advanced process nodes, which is critical for embedded NVM in MCUs and SoCs.
Temperature Range: ReRAM demonstrates better data retention at elevated temperatures compared to Flash, making it more suitable for high-temperature industrial applications.
Byte Addressability: ReRAM can be made byte-addressable without an erase-before-write requirement — enabling storage-class memory use cases where the non-volatile memory is accessed directly by the processor like SRAM, eliminating the need for a file system layer.
Current Commercial Status of ReRAM — Where Is It Being Deployed?
As of 2026, ReRAM is in early commercial deployment, primarily as embedded NVM (eNVM) integrated into MCUs and SoCs on advanced CMOS process nodes. The ability to integrate ReRAM on CMOS logic processes (without specialized process additions required by Flash) makes it attractive for embedded NVM in systems that want to use advanced nodes for their compute logic while maintaining integrated non-volatile storage.
Weebit Nano's ReRAM IP is being licensed to foundries and chip companies for integration into their processes. TSMC, UMC, and other foundries are evaluating ReRAM as an embedded NVM option for their MCU and IoT chip customers. Weebit Nano's appearance at Embedded World 2026 reflects the active push to get ReRAM into volume embedded applications.
Other ReRAM players include Crossbar (embedded NVM for microcontrollers), Silicon Storage Technology / Microchip (OTP and MTP ReRAM variants), and YMTC (exploring ReRAM for storage applications in China).
The AI Angle — ReRAM as Compute-in-Memory
Beyond conventional storage applications, ReRAM has attracted significant research interest as a compute-in-memory (CIM) technology. In a CIM implementation, the matrix multiplication operations that dominate neural network inference are performed directly in the memory array — by exploiting the analog physics of the resistive elements — rather than reading data to a separate compute unit for processing.
In a ReRAM CIM array, neural network weights are stored as resistance values in the array. Input activation values are applied as voltages to the word lines. The resulting currents on the bit lines implement Ohm's law (I = V/R) and Kirchhoff's current law (currents sum at the output node) — which together perform the weighted sum operation at the core of neural network inference, in a single step, with no data movement.
This approach can achieve dramatically better energy efficiency for neural network inference compared to conventional digital compute architectures, because it eliminates the dominant energy cost of moving data between memory and compute. For edge AI applications in ultra-low-power IoT and embedded systems — where the energy cost of inference is measured in microjoules and the power budget is measured in microwatts — compute-in-memory with ReRAM could be the enabling technology for always-on AI processing at the sensor level.
What This Means for Industrial Embedded System Design
For engineers designing industrial embedded systems in 2026–2028, ReRAM is not yet a primary component choice for most applications — Flash remains the dominant non-volatile memory technology, with a mature ecosystem of devices, development tools, and support. But the trajectory is clear, and several design decisions are worth making with ReRAM availability in mind.
Systems with high write frequency requirements — data loggers, configuration stores that change frequently, AI model parameter caches — should evaluate Flash alternatives proactively. Designs that require extreme temperature operation should investigate ReRAM options as they become commercially available. And system architects designing for future AI-enabled edge devices should be aware that compute-in-memory architectures enabled by ReRAM may change the power and performance characteristics of embedded inference significantly within the next 3–5 years.
Why endurance is a failure mode rather than a line on a datasheet
The way I approach system design is to assume components will fail rather than treat failure as a remote possibility, and to ask what the system does when they do. Non-volatile memory is a good illustration, because it is one of the few components that fails on a schedule you can calculate in advance and then routinely fail to calculate.
A device that writes a record every few seconds for years accumulates a very large number of write cycles, and if that traffic lands repeatedly on the same region, the endurance limit is not a distant abstraction — it is a date. Wear levelling exists precisely because of this, but wear levelling is a mitigation layered on top of a constraint, and it has to be implemented, configured and reasoned about. Memory technology with materially higher endurance changes the shape of that problem rather than just improving a number, because it moves the failure date far enough out that the mitigation stops being load-bearing.
The second property that matters more than it appears to is write behaviour during power loss. Industrial equipment loses power — not as an exception but as a normal event: emergency stops, supply interruptions, a technician throwing a breaker. A write in progress when the rail collapses is a classic source of corruption, and a memory that completes writes faster and at lower voltage narrows that window. It does not close it. It should not be treated as a substitute for designing the storage layer to survive an interruption at any point — a journalled or transactional write path, a way to detect a partial record, and a defined behaviour on encountering one.
The third is that the storage layer should not be able to take the machine down with it. My general preference is to separate critical control functions from non-critical services so that a failure in the second does not automatically become a failure in the first. Logging and telemetry are, in almost every machine I would design, non-critical: a full or degraded log should mean lost visibility, not a stopped mechanism. Where the storage genuinely is critical — calibration data, safety parameters, configuration required to start safely — it deserves redundancy and validation on read, whatever the underlying technology.
Which is the practical way to read a technology like ReRAM: it makes a known failure mode much less pressing, and that is genuinely valuable. It does not remove the obligation to design for the failure, because the system still has to behave sensibly on the day the memory does something unexpected — and improved components change how often that day arrives, not what happens when it does.
Conclusion
ReRAM is not a distant technology. It is entering commercial deployment now, on the strength of endurance, write speed and CMOS process compatibility advantages over embedded Flash — advantages that matter most precisely at the advanced nodes where embedded Flash becomes difficult to integrate. The longer-term compute-in-memory possibility is a more fundamental shift, and a more speculative one.
For embedded and industrial work, the near-term significance is narrower and more concrete: a technology that pushes a predictable wear-out failure far enough into the future that it stops shaping the design around it. That is worth having. It is worth having on top of a storage layer that already assumes interruption and failure — not instead of one.